module FETCH (
        //      Inputs
        pc_in, createdump, clk, rst,
        //      Outputs
        inst, addr_out,err
        );

        input   [15:0]  pc_in;
        input           clk,rst;
        input           createdump;

        output  [15:0]  inst;
        output  [15:0]  addr_out;
        output          err;

        wire    [15:0]  pc_out;
        pc      pc      
        (
                .rst ( rst ),
                .clk ( clk ),
                .pc_en ( 1'b1 ),
                .pc_in ( pc_in ),
                .pc_out ( pc_out )
        );
        alu     adder
        (
                .op1 ( pc_out ),
                .op2 ( 16'H0002 ),
                .aluctr ( 4'b0000 ),
                .out ( addr_out ),
                .carry_out ()
        );
        memory2c        ist_mem
        (
                .data_out ( inst ),
                .data_in (),
                .addr ( pc_out ),
                .clk ( clk ),
                .rst ( rst ),
                .enable ( 1'b1 ),
                .wr ( 1'b0 ),
                .createdump ( createdump )
        );
endmodule
